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74ALVC16244DL View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
74ALVC16244DL 2.5V/3.3V 16-bit buffer/line driver (3-State) Philips
Philips Electronics Philips
74ALVC16244DL Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors
16-bit buffer/line driver (3-State)
Product specification
74ALVC16244/
74ALVCH16244
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74ALVCH16244 only)
Output drive capability 50transmission lines @ 85°C
Current drive ±24 mA at 3.0 V
PIN CONFIGURATION
1OE 1
1Y0 2
1Y1 3
GND 4
1Y2 5
1Y3 6
VCC 7
2Y0 8
2Y1 9
GND 10
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 2A0
40 2A1
39 GND
DESCRIPTION
The 74ALVC16244(74ALVCH16244) is a 16-bit non-inverting
buffer/line driver with 3-State outputs. The device can be used as
four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-State
outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH on nOE causes the outputs to assume a high impedance
OFF-state.
The 74ALVCH16244 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
The 74ALVC16244 has 5V tolerant inputs.
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
VCC 18
4Y0 19
4Y1 20
GND 21
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 VCC
30 4A0
29 4A1
28 GND
4Y2 22
27 4A2
4Y3 23
26 4A3
4OE 24
25 3OE
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
SW00194
TYPICAL
tPHL/tPLH
CI
CPD
Propagation delay
An to Yn
Input capacitance
Power dissipation capacitance per buffer
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
1.9
1.9
5.0
Outputs enabled
25
Outputs disabled
4
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs.
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVC16244 DL
–40°C to +85°C
74ALVC16244 DGG
–40°C to +85°C
74ALVCH16244 DL
–40°C to +85°C
74ALVCH16244 DGG
NORTH AMERICA
AC16244 DL
AC16244 DGG
ACH16244 DL
ACH16244 DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
1998 Jun 29
2
853-2082 19638
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