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74ALVCH16373DGG View Datasheet(PDF) - Philips Electronics

Part Name
Description
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74ALVCH16373DGG
Philips
Philips Electronics Philips
74ALVCH16373DGG Datasheet PDF : 12 Pages
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Philips Semiconductors
16-bit D-type transparent latch (3-State)
Product specification
74ALVCH16373
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50transmission lines @ 85°C
Current drive ±24 mA at 3.0 V
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. One latch enable (LE) input and one output enable
(OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
SW00066
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
CI
CPD
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Input capacitance
Power dissipation capacitance per latch
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
2.1
2.1
2.2
2.2
5.0
Outputs enabled
16
Outputs disabled
10
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH16373 DL
–40°C to +85°C
74ALVCH16373 DGG
NORTH AMERICA
ACH16373 DL
ACH16373 DGG
DWG NUMBER
SOT370-1
SOT362-1
1999 Sep 20
2
853-2086 22418
 

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