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24C256 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Fairchild
Fairchild Semiconductor Fairchild
24C256 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Bus Timing
tF
tHIGH
tLOW
SCL
SDA
tSU:STA
tHD:STA
tHD:DAT
;;IN
tAA
SDA
OUT
Note 3: SCL = Serial Clock Data
SDA = Serial Data I/O
BACKGROUND INFORMATION (IIC Bus)
The IIC bus allows synchronous bidirectional communication be-
tween Transmitter/Receiver using the SCL (clock) and SDA (Data
I/O) lines. All communication must be started with a valid START
condition, concluded with a STOP condition and acknowledged by
the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
control byte, must follow the START condition. For EEPROMs, the
first 4-bit of the control byte is 1010 binary for READ and WRITE
operations. This is then followed by the device selection bits A2, A1
and A0, and acts as the three most significant bits of the word
address.The final bit in the control byte determines the type of
operation performed (READ/WRITE). A "1" signifies a READ while
a "0" signifies a WRITE. The control byte is then followed by two bytes
that define the word address, which is then followed by the data byte.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
512K bits (64K bytes). EEPROM memory addressing is controlled
by hardware configuring the A2, A1, and A0 pins (Device Address
pins) with pull-up or pull-down resistors. ALL UNUSED PINS
MUST BE GROUNDED (tied to VSS).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]
Pin Description
SERIAL CLOCK (SCL)
Definitions
Word
Page
Master
Slave
Transmitter
Receiver
8 bits (byte) of data
64 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.
Any IIC device CONTROLLING the transfer of
data (such as a microcontroller).
Device being controlled (EEPROMS are
always considered Slaves).
Device currently SENDING data on the bus
(may be either a Master or Slave).
Device currently receiving data on the bus
(Master or Slave).
The SCL input is used to clock all data into and out of the device.
tR
tLOW
tSU:DAT
tSU:STO
tDH
tBUF
DS800023-3
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data to and from the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM address for multiple device configura-
tion. A total of eight different devices can be attached to the same
SDA bus.
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the entire
array of the memory will not be executed. READ operations are
always available.
If WP is tied to VSS or left floating (unconnected), normal memory
operation is enabled for READ/WRITE over the entire 256K bit
memory array.
This feature allows the user to assign the entire array of the memory
as ROM, which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
The FM24C256xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is con-
trolled is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. There-
fore, the FM24C256xxx is considered a slave in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and are reserved for
indication of start and stop conditions. Refer to Figures 1 and 2.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C256xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C256xxx to place the device in
the standby power mode.
FM24C256 rev. B.3
6
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