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24C256 View Datasheet(PDF) - Fairchild Semiconductor

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24C256 Datasheet PDF : 12 Pages
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June 2000
FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to VCC.
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features
I Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
I Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
I 2-wire IIC serial interface
I 64 byte page write mode
I Max write cycle time of 6ms byte/page
I 40 years data retention
I Endurance: 100,000 data changes
I Hardware write protect for entire array
I Schmitt trigger inputs for noise suppression
I Electrostatic discharge protection > 4000V
I 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory
for CSP package availability
Block Diagram
VCC
WP
SDA
SCL
A2
A1
A0
WRITE
LOCKOUT
START
STOP
LOGIC
START CYCLE
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
R/W
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
YDEC
CK
DIN
DATA REGISTER
DOUT
DS800023-1
© 2000 Fairchild Semiconductor International
1
FM24C256 rev. B.3
www.fairchildsemi.com
 

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