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24LC014T View Datasheet(PDF) - Microchip Technology

Part NameDescriptionManufacturer
24LC014T I2C™ Serial EEPROM Family Data Sheet Microchip
Microchip Technology Microchip
24LC014T Datasheet PDF : 42 Pages
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24AAXX/24LCXX/24FCXX
8.0 READ OPERATION
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX contains an address counter that maintains
the address of the last byte accessed, internally incre-
mented by ‘1’. Therefore, if the previous read or write
operation was to address ‘n’ (n is any legal address),
the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX issues an acknowledge and transmits the
8-bit data byte. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the byte address must first
be set. This is done by sending the byte address to the
24XX as part of a write operation (R/W bit set to ‘0).
Once the byte address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address counter is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX will then issue an acknowledge and transmit the
8-bit data byte. The master will not acknowledge the
transfer but does generate a Stop condition, which
causes the 24XX to discontinue transmission
(Figure 8-2 and Figure 8-3). After a random Read
command, the internal address counter will increment
to the next address location.
FIGURE 8-1:
S
Bus Activity
T
A
Master
R
T
SDA Line S
Bus Activity
CURRENT ADDRESS
READ
Control
Byte
A
C
K
S
Data
T
Byte
O
P
P
N
O
A
C
K
FIGURE 8-2:
Bus Activity
Master
SDA Line
Bus Activity
RANDOM READ: 128-BIT TO 16 KBIT DEVICES
S
T
Control
A
R
Byte
T
Address
Byte (n)
S
T
Control
A
R
Byte
T
Data
Byte
S
T
O
P
S
S
P
A
A
C
C
K
K
A
N
C
O
K
A
C
K
FIGURE 8-3:
RANDOM READ: 32 TO 512 KBIT DEVICES
Bus Activity
Master
S
T
A
Control
R
Byte
T
High Order
Address Byte
S
Low Order
T
A
Address Byte R
T
Control
Byte
Data
S
T
Byte
O
P
SDA Line
S
S
P
Bus Activity
A
A
A
C
C
C
K
K
K
A
N
C
O
K
A
C
K
© 2007 Microchip Technology Inc.
DS21930B-page 19
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