24LC014T View Datasheet(PDF) - Microchip Technology

Part Name

Description

View to exact match

24LC014T

I2C™ Serial EEPROM Family Data Sheet

Microchip Technology 

24AAXX/24LCXX/24FCXX

5.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Note: During a write cycle, the 24XX will not

acknowledge commands.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end-of-

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX) will leave the data line

high to enable the master to generate the Stop

condition (Figure 5-2).

FIGURE 5-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(D)

SCL

(C) (A)

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

FIGURE 5-2:

ACKNOWLEDGE TIMING

Acknowledge

bit

SCL

1

2

3

4

5

6

7

8

9

1

2

3

SDA

Data from transmitter

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Data from transmitter

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

DS21930B-page 12

© 2007 Microchip Technology Inc.

Share Link: