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FW21555AA View Datasheet(PDF) - Intel

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FW21555AA Datasheet PDF : 60 Pages
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Documentation Changes
9.
Issue:
Section 16.1Byte Offset of D7:D6 needs updating
Refer to Section 16.1, Table 16-1, on page 16-4, the D7:D6 Byte Offset Register Name and Reset
Value row. Add the following information to the Register Name and Reset Value (Hex) columns.
D5
Secondary SERR# Disable
00
Y
Y
Y
Determined by
D7:D6
Mode Settings Configuration
Register
Parallel ROM
Strapping
N
Y
Options
DB:D8
Reset Control
0000
Primary
Y
Affected Docs: 21555 Non-Transparent PCI-to-PCI Bridge Advance Information Users Manual (278321).
10.
Remove reference to CLS=4
Issue:
Remove the following lines:
Section 2.3.1.4, Page 2-14 delete A full cache line threshold is used for CLS=4.
Section 2.4.2.2, Table 2-25, Page 2-36. Delete two sentences: When CLS=4 a full cache line
threshold is used..
Affected Docs: 21555 Non-Transparent PCI-to-PCI Bridge Advance Information Users Manual (278321)
11.
Issue:
JTAG Action during Hot insertion
Change Table 12-1 row 3 to be as follows:
The JTAG test mode select pin, tms causes state transitions in the Test Access Port (TAP) controller. The tms
signal is pulled high by a weak pull-up resistor internal to the device. If this pin is low while t_rst_l is low the
tms
I
device can enter an unsupported mode. Other devices that are not on early power and are connected to the
JTAG Scan Chain, pull tms low during Hot Insertion causing the 21555 to enter the unsupported mode.
During the Hot Insertion isolate this signal from other JTAG devices on the circuit board or JTAG scan chain.
Affected Docs: 21555 Non-Transparent PCI-to-PCI Bridge Advance Information User Manual (278321).
12.
Issue:
Internal and External Signal Terminations
Change Table 12-1 rows 1 and 4 to be as follows:
tck
I
trst_l I
JTAG boundary-scan clock. Signal tck is the JTAG logic control clock. This pin has an internal weak pull-down
resistor.
JTAG TAP reset and disable. When low, JTAG is disabled and the TAP controller is asynchronously forced
into the reset state, which in turn asynchronously initializes other test logic. An unterminated trst_l is pulled
high by a weak pull-up resistor internal to the device. The TAP controller must be reset before the JTAG
circuits can function. For normal JTAG TAP port operation, this signal must be high.
Prior to normal 21555 operation, this signal must be strobed low or pulled low with a 1kresistor.
Affected Docs: 21555 Non-Transparent PCI-to-PCI Bridge Advance Information User Manual (278321).
20
21555 Non-Transparent PCI-to-PCI Bridge Specification Update
 

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