FW21555AA View Datasheet(PDF) - Intel
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FW21555AA Datasheet PDF : 60 Pages
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Table 12. Reset Timing Specifications (Sheet 2 of 2)
Symbol Parameter
Trrsus
Trrval
Trrsu
Trrh
s_req64_l asserted to s_rst_l deasserted
s_rst_l to s_req64_l deasserted delay time
REQ64# to RST# deasserting setup time
REQ64# from RST# deasserting hold time
a. Applies to rising (deasserting) edge only.
3.4.4
Serial ROM Timing Specifications
Table 13 shows the serial ROM timing specifications.
Table 13. Serial ROM Timing Specifications
Symbol
Tscval
Tson
Tsoff
Tssu
Tsh
Tsmcs
Tscyc
Parameter
pclk to pr_ad[0] serial ROM clock valid
pr_ad float to active delay
pr_ad active to float delay
pr_ad[1] di to pr_ad[0] serial ROM clock setup time
pr_ad[1] to pr_ad[0] serial ROM clock hold time
sr_cs minimum low time
pr_ad[0] serial ROM clock cycle time
3.4.5
Parallel ROM Timing Specifications
Table 14 shows the parallel ROM timing specifications.
Table 14. Parallel ROM Timing Specifications
Symbol
Tpas
Tpcc
Tpacs
Tpcsl
Tpcrw
Tprs
Tprh
Tprv
Parameter
pr_ale_l setup to pr_clk rising
pr_clk cycle time
pr_ale_l rising to pr_cs_l falling
pr_cs_l low
pr_cs_l falling to pr_rd_l or pr_wr_l falling
pr_ad setup time to pr_rd_l rising
pr_ad hold time from pr_rd_l rising
pr_clk rising to pr_ad valid
Minimum Maximum Unit
10*Tcyc
—
nsa
0 Tcyc
—
nsa
Tcyc
—
ns
0
50
ns
Minimum Maximum Unit
—
14
ns
2
—
ns
—
28
ns
400
—
ns
20
—
ns
400
—
ns
1000
—
ns
Minimum Maximum Unit
30
—
ns
60
—
ns
25
—
ns
200
—
ns
25
—
ns
180
—
ns
0
—
ns
0
15
ns
Datasheet
27
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