21143 View Datasheet(PDF) - Intel

Part Name

Description

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21143

PCI/CardBus 10/100 Ethernet LAN Controller

Intel 

21143

3.10

3.10.1

Boot ROM Port Timing

This section describes the boot ROM port timing.

Boot ROM Read Timing

Figure 18 shows the boot ROM read timing characteristics, and Table 33 lists the boot ROM read

timing limits.

Tads Tadh Tads Tadh Tavqv

br_ad<7:0>

Address = <7:2>

oe = O, we = 1

Address <15:8>

Data <7:0>

Valid

br_a<1>

Address <1>

br_a<0>

br_ce_l

Address <17> Address <16>

Address <0>

Telqx

Telqv

Toh

Tehqz

Tavav

A5993-01

Figure 18. Boot ROM Read Timing Diagram

Table 33. Boot ROM Read Timing Specifications

Symbol

Parameter

Tavav

Read cycle time

Tavqv

Address to output delay

Telqv

Telqx1

Tehqz1

br_ce_l to output delay

br_ce_l to output low impedance

br_ce_l going high to output high impedance

Toh

Output hold from br_ce_l change

Tads

Address setup to latch enable high

Tadh

Address hold from latch enable high

1. Parameter design guarantee.

Minimum Maximum Unit

240

—

ns

—

240

ns

—

240

ns

0

—

ns

—

55

ns

0

—

ns

30

—

ns

30

—

ns

Preliminary Datasheet

37

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