21143 View Datasheet(PDF) - Intel
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21143 Datasheet PDF : 52 Pages
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21143
Table 4. Functional Description of 21143 Signals (Sheet 4 of 6)
Signal
Type Pin Number
Description
mii/
sym_rxd<3:0>
mii/sym_tclk
mii/
sym_txd<3:0>
mii_txen/
sym_txd<4>
par
pci_clk
perr_l
req_l
rst_l
serr_l
sr_ck
sr_cs
sr_di
sr_do
I
130, 131,
132,133,
Four parallel receive data lines. This data is driven by an external
PHY that attached the media and should be synchronized with the
mii_rclk signal.
I
124
Supports the 25-MHz or 2.5-MHz transmit clock supplied by the
external PMD device. This clock should always be active.
O
119, 120, 121,
122
Four parallel transmit data lines. This data is synchronized to the
assertion of the mii_tclk signal and is latched by the external PHY on
the rising edge of the mii_tclk signal.
In MII mode (CSR6<18>=1, CSR6<23>=0), this pin functions as
transmit enable. It indicates that a transmission is active on the MII
port to an external PHY device.
O
123
In SYM mode, this pin functions as transmit data. This line along with
the four data transmit lines (sym_txd<3:0>) provides five parallel data
lines in symbol form. The data is synchronized to the rising edge of
the sym_tclk signal.
Parity is calculated by the 21143 as an even parity bit for the 32-bit ad
and 4-bit c_be_l lines.
I/O
59
During address and data phases, parity is calculated on all the ad
and c_be_l lines whether or not any of these lines carry meaningful
information.
The clock provides the timing for the 21143 related PCI bus
I
19
transactions. All the bus signals are sampled on the rising edge of
pci_clk. The supported range of the clock frequency is 20 MHz to
33 MHz.
Parity error asserts when a data parity error is detected.
The 21143 asserts perr_l when a data parity error is detected in either
a master-read or a slave-write operation.
I/O
57
When the 21143 is the bus master and a parity error is detected, the
21143 asserts both CSR5 bit 13 (fatal bus error) and CFCS bit 24
(data parity report). Next, it completes the current data burst
transaction, then stops operation. After the host clears the fatal error
bit in CSR5, the 21143 continues its operation.
O
22
Bus request is asserted by the 21143 to indicate to the bus arbiter
that it wants to use the bus.
Resets the 21143 to its initial state. This signal must be asserted for
I
16
at least 10 active PCI clock cycles. When in the reset state, all PCI
output pins are put into tristate and all PCI O/D signals are floated.
If an address parity error is detected and CFCS bit 8 (serr_l enable) is
enabled, 21143 asserts both serr_l (system error) and CFCS bit 30
O/D
58
(signal system error).
When an address parity error is detected, system error asserts two
clocks after the failing address.
O
114
Serial ROM clock signal. This pin provides a serial clock output for
the serial ROM.
O
115
Serial ROM chip-select signal. This pin provides a chip select for the
serial ROM.
O
113
Serial ROM data-in signal. This pin serially shifts the write data from
the 21143 to the serial ROM device.
I
112
Serial ROM data-out signal. This pin serially shifts the read data from
the serial ROM device to the 21143.
Preliminary Datasheet
13
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