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BR9010FV View Datasheet(PDF) - ROHM Semiconductor

Part Name
Description
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BR9010FV Datasheet PDF : 17 Pages
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Memory ICs
(2) Timing chart
CS
SK
DI
DO
BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F /
BR9040 / BR9040F
tCSS
tWL
tDIS
tPD
tWH
tDIH
tPD
tCS
tCSH
tOH
WC
• Data is read in on the rising edge of SK. Data is output in synchronism with the SK falling edge.
• During a READ operation, data is output from DO in synchronization with the SK rise.
• WC is related to the write command only. Read, erase / write enable, erase / write disable commands can be executed irrespective of the state of WC.
(3) Writing enabled / disabled
H
1
4
SK L
H
CS L
8
12
16
ENABLE = 1 1
DISABLE = 0 0
H
DI
L
10100 0
High-Z
DO
H
R/B
WC H or L
Fig.1
1) When the power supply is turned on, the latch used to acknowledge writing is reset in the same way as when the
write disable command is executed. Before entering the write mode, the write enabled mode must first be entered.
Once the write enabled mode has been recognized, it remains valid until the write disabled mode is entered, or
the power supply is turned off.
2) The clock is no longer necessary after the first 16 clock pulses have been received. Any subsequent input will be
ignored.
3) WC does not exist for either the write enabled or write disabled command, so WC may be either HIGH or LOW
when the command is being input.
4) Commands are received in these modes by means of 8-bit operating codes. Please be aware that, after an oper-
ating code has been entered, commands will not be canceled even if CS is set to HIGH. (To cancel a command,
either turn off the power supply, or input the command once again.)
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