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ST24FC21B View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24FC21B 1 Kbit (x8) Dual Mode Serial EEPROM for VESA PLUG & PLAY ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24FC21B Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
16
12
8
4
0
10
VCC
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
RL
SDA
MASTER
SCL
RL
CBUS
1000
CBUS
AI01665
When the ST24FC21 (or the ST24FC21B or the
ST24FW21) first switches to the I2C mode (VESA
DDC2B mode), it enters a transition state which is
functionally identical to I2C operation. But, if the
ST24FC21 (or the ST24FC21B or the ST24FW21)
does not receive a valid I2C sequence, that is a
START condition followed by a valid Device Select
co de (10 10XXX RW f o r ST 2 4F C 21 an d
ST24FW21; 1010000 RW for ST24FC21B), within
either 128 VCLK periods or a period of time of
tRECOVERY ( appr ox imat ely 2 seconds), the
ST24FC21 (or the ST24FC21B or the ST24FW21)
will revert to the Transmit-Only mode (VESA DDC1
mode).
If the ST24FC21 (or the ST24FC21B or the
ST24FW21) decodes a valid I2C Device Select
code, it will lock into I2C mode. Under this condition,
signals applied on the VCLK input will not disturb
READ access from the ST24FC21 (or the
ST24FC21B or the ST24FW21). For WRITE ac-
cess, refer to the Signal Description paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This means that,
after each high to low transition on SCL, the mem-
ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new tRECOVERY delay.
SIGNAL DESCRIPTIONS
I2C Serial Clock (SCL). The SCL input pin is used
to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 6).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 6).
Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the ST24xy21
is in Transmit Only mode.
For the ST24LC21B and the ST24FC21 or
ST24FC21B Only, the VCLK offers also a Write
Enable (active high) function when the ST24LC21B
and the ST24FC21 or ST24FC21B are in I2C bidi-
rectional mode.
Write Control (WC). An hardware Write Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro-
neous erase/write cycle. The Write Control signal
is used to enable (WC = VIL) or disable (WC = VIH)
the internal write protection. When unconnected,
the WC input is internally tied to VSS by a 100k ohm
pull-down resistor and the memory is write pro-
tected.
DEVICE OPERATION
7/22
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