|ST24FC21M6TR||1 Kbit (x8) Dual Mode Serial EEPROM for VESA PLUG & PLAY|
|ST24FC21M6TR Datasheet PDF : 22 Pages |
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms
Transmit Only Mode
- Temporary Bi-Directional Mode
(ST24FC21 and ST24FW21)
- Locked Bi-Directional Mode
(ST24LC21B and ST24LW21)
- Locked Bi-Directional
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
I2C Bidirectional Mode
The ST24xy21 can be switched from Transmit Only
mode to I2C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4).
– When the ST24LC21B (or the ST24FC21 or
the ST24FC21B) is in the I2C Bidirectional
mode, the VCLK input (pin 7) enables (or inhib-
its) the execution of any write instruction: if
VCLK = 1, write instructions are executed; if
VCLK = 0, write instructions are not executed.
– When the ST24LW21 (or the ST24FW21) is in
the I2C Bidirectional mode, the Write Control
(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.
The ST24xy21 is compatible with the I2C standard,
two wire serial interface which uses a bidirectional
data bus and serial clock. The ST24xy21 carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding
to the I2C bus definition. The ST24LC21B carries a
unique device identification code (1010.0000 RW)
named Device Select code corresponding to the
I2C bus definition.
The ST24xy21 behaves as a slave device in the
I2C protocol with all memory operations synchro-
nized by the serial clock SCL. Read and write
operations are initiated by a START condition gen-
erated by the bus master. The START condition is
followed by a stream of 7 bits, plus one read/write
bit and terminated by an acknowledge bit.
When data is written into the memory, the
ST24xy21 responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledge the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE descrip-
tions in the following pages).
Power On Reset: VCC lock out write protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Error Recovery Modes available in the
ST24FC21, ST24FC21B and the ST24FW21
|Direct download click here|
|Share Link :|