AD9142A-M5375-EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

AD9142A-M5375-EBZ

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

AD9142A

Data Sheet

Reg

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

FIFO_LEVEL_ [7:0] Reserved

CONFIG

INTEGER_FIFO_LEVEL_REQUEST

Reserved

FRACTIONAL_FIFO_LEVEL_REQUEST

0x40 RW

FIFO_LEVEL_ [7:0] Reserved

READBACK

INTEGER_FIFO_LEVEL_READBACK

Reserved

FRACTIONAL_FIFO_LEVEL_READBACK 0x00 R

FIFO_CTRL [7:0]

Reserved

FIFO_SPI_

RESET_ACK

FIFO_SPI_

RESET_

REQUEST

0x00 RW

DATA_

FORMAT

[7:0] DATA_

FORMAT

DATA_

PAIRING

DATA_BUS_

INVERT

Reserved

DATA_BUS_ 0x00 RW

WIDTH

DATAPATH_ [7:0] INVSINC_

CTRL

ENABLE

NCO_ENABLE IQ_GAIN_ADJ_ IQ_PHASE_ADJ_ Reserved

DCOFFSET_ ENABLE

ENABLE

FS4_

NCO_

MODULATION_ SIDEBAND_

ENABLE

SEL

SEND_IDATA 0x00 RW

_TO_QDAC

INTERPOLATION [7:0]

_CTRL

Reserved

INTERPOLATION_MODE 0x00 RW

OVER_

[7:0]

THRESHOLD_

CTRL0

THRESHOLD_LEVEL_REQUEST_LSB

0x00 RW

OVER_

[7:0]

THRESHOLD_

CTRL1

Reserved

THRESHOLD_LEVEL_REQUEST_MSB

0x00 RW

OVER_

[7:0] ENABLE_ IQ_DATA_

THRESHOLD_

PROTECTION SWAP

CTRL2

Reserved

SAMPLE_WINDOW_LENGTH

0x00 RW

INPUT_

[7:0]

POWER_

READBACK_LSB

INPUT_POWER_READBACK_LSB

0x00 R

INPUT_POWER_ [7:0]

READBACK_

MSB

Reserved

INPUT_POWER_READBACK_MSB

0x00 R

NCO_CTRL

[7:0] Reserved

NCO_FRAME_ SPI_NCO_

UPDATE_ACK PHASE_RST_

ACK

SPI_NCO_

PHASE_

RST_REQ

Reserved

NCO_SPI_

NCO_SPI_ 0x00 RW

UPDATE_ACK UPDATE_REQ

NCO_FREQ_ [7:0]

TUNING_

WORD0

NCO_FTW0

0x00 RW

NCO_FREQ_ [7:0]

TUNING_

WORD1

NCO_FTW1

0x00 RW

NCO_FREQ_ [7:0]

TUNING_

WORD2

NCO_FTW2

0x00 RW

NCO_FREQ_ [7:0]

TUNING_

WORD3

NCO_FTW3

0x10 RW

NCO_PHASE_ [7:0]

OFFSET0

NCO_PHASE_OFFSET_LSB

0x00 RW

NCO_PHASE_ [7:0]

OFFSET1

NCO_PHASE_OFFSET_MSB

0x00 RW

IQ_PHASE_ [7:0]

ADJ0

IQ_PHASE_ADJ_LSB

0x00 RW

IQ_PHASE_ [7:0]

ADJ1

Reserved

IQ_PHASE_ADJ_MSB

0x00 RW

LVDS_IN_

[7:0]

PWR_DOWN_0

PWR_DOWN_DATA_INPUT_BITS

0x00 RW

IDAC_DC_ [7:0]

OFFSET0

IDAC_DC_OFFSET_LSB

0x00 RW

IDAC_DC_ [7:0]

OFFSET1

IDAC_DC_OFFSET_MSB

0x00 RW

QDAC_DC_ [7:0]

OFFSET0

QDAC_DC_OFFSET_LSB

0x00 RW

QDAC_DC_ [7:0]

OFFSET1

QDAC_DC_OFFSET_MSB

0x00 RW

IDAC_GAIN_ [7:0]

ADJ

Reserved

IDAC_GAIN_ADJ

0x20 RW

QDAC_GAIN_ [7:0]

ADJ

Reserved

QDAC_GAIN_ADJ

0x20 RW

GAIN_STEP_

CTRL0

Reserved

RAMP_UP_STEP

0x01 RW

Rev. A | Page 50 of 72

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