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ST24C04 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24C04 Serial I2C Bus EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24C04 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ST24/25C04, ST24/25W04
ory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytes of
data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master.
Figure 7. Memory Protection
Protect Location
8 byte
boundary
address
Protect Flag
Enable = 0
Disable = 1
b7
1FFh
b3 b2
XX
Block 1
100h
Block 0
AI00855B
Figure 8. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by ST24xxx
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send
Byte Address
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01099B
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