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O9039A385IZWSRQ1 Automotive Power Management Unit (PMU) for Processor TI
Texas Instruments TI
O9039A385IZWSRQ1 Datasheet PDF : 109 Pages
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TPS659038-Q1, TPS659039-Q1
SWCS095K – AUGUST 2013 – REVISED JANUARY 2018
www.ti.com
Changes from Revision D (October 2014) to Revision E
Page
• Added caution statement to the Specifications section ........................................................................ 18
• Added caution statement to the Specifications section ........................................................................ 37
Changes from Revision C (June 2014) to Revision D
Page
• Deleted the export control notice from the data sheet .......................................................................... 2
• Removed all notions of (3.6V tolerance) from VRTC digital pins without fail-safe feature ................................ 17
• Changed Replaced LDOVRTCmax + 0.3 notion with actual value of 2.15 under the ABS Max Rating table for
VRTC digital input pins ............................................................................................................. 18
• Changed Replaced LDOVRTCmax notion with actual value of 1.85 under the ROC table for OSC16MIN and
VRTC digital input pins ............................................................................................................. 19
• Updated typical IQ(on) value of LDOUSB-IN1 from 30µA to 45µA in accordance with characterization data ......... 21
• Added Caution clause to describe the scenario which may cause unexpected shutdown of the PLL, and the
actions to recover from such fault condition. .................................................................................... 73
• Added comments for the ideal SMPS voltage-spike measurement condition under Layout Guidance section. ....... 95
Changes from Revision B (June 2014) to Revision C
Page
• Updated Latch Up Current Class specification format and separated LDOVANA_OUT pin specification from all
other pins............................................................................................................................. 19
• Updated typical value of high-side FET rDS(on) from 50mΩ to 115mΩ for all multi-phase SMPSs ....................... 22
• Updated typical value of low-side FET rDS(on) from 39mΩ to 30mΩ for all multi-phase SMPSs .......................... 22
• Updated typical value of High-side FET rDS(on) from 50mΩ to 115mΩ for all single-phase SMPSs except SMPS 8
& 9 .................................................................................................................................... 24
• Updated typical value of high-side FET rDS(on) from 110mΩ to 180mΩ for SMPS8 & 9 ................................... 24
• Updated typical value of low-side FET rDS(on) from 39mΩ to 30mΩ for all single-phase SMPSs except SMPS 8 &
9 ...................................................................................................................................... 24
• Updated the typical value of CLK32KGO output buffer rise and fall time based on characterization data. ............ 25
• Updated the min and max value of CLK32KGO1V8 output buffer rise and fall time based on simulation data. ...... 25
• Added comments on limitation of Vout/Vin ratio and Vin monitor and shut down mechanism when a SMPS
converter is in ECO mode. ......................................................................................................... 40
Changes from Revision A (May 2014) to Revision B
Page
• Corrected the default state of the NSLEEP pin to PPU under Pin Function table.......................................... 12
• Corrected the voltage range for the GPADC_IN0 and GPADC_IN1 pins under the Recommended Operating
Conditions table ..................................................................................................................... 19
• Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in multi-phase
configuration ......................................................................................................................... 22
• Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in single-phase
configuration ......................................................................................................................... 23
• Added device Current Consumption specification for Sleep Mode when VSYS = 5.25V ................................. 28
• Added paragraph with regards to the importance of VSYS being the first supply available to the device. ............ 39
• Added approximate power rail shut down time from a short detection....................................................... 43
• Added approximate wait time for the device to reach OFF state from No Supply state. .................................. 68
• Added a paragraph under the Application Information section to emphasize the importance of operating the
device under ROC, and encourage customers to consider thermal management, power sequencing and layout
strategy to maximize device performance........................................................................................ 84
Changes from Original (April 2014) to Revision A
Page
• Added option to float the VPROG pin when it is configured as an input pin ............................................... 12
• Updated Output Type of I2C2_SDA_SDO pin to specify Push-pull type when the pin is configured in SPI mode .... 17
• Corrected the minimum voltage level for all SMPS-related input pins to match VSYS minimum input level in
Recommended Operating Conditions ........................................................................................... 19
6
Revision History
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