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O9039A385IZWSRQ1 Automotive Power Management Unit (PMU) for Processor TI
Texas Instruments TI
O9039A385IZWSRQ1 Datasheet PDF : 109 Pages
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TPS659038-Q1, TPS659039-Q1
SWCS095K – AUGUST 2013 – REVISED JANUARY 2018
www.ti.com
5 Specifications
5.1 Absolute Maximum Ratings
See(1) (2).
MIN
MAX
UNIT
Voltage on VCC1 pins
–0.3
6
V
Voltage on VCC_SENSE, VCC_SENSE2 pins
–0.3
7
V
All LDOs and SMPS supply voltage input pins (except LDOUSB_IN2)
–0.3
6
V
Voltage on SMPSx_SW pins, 10 ns transient
–2
7
V
All SMPS-related input pins _FDBK
–0.3
3.6
V
LDOUSB regulator LDOUSB_IN2 input voltage
–0.3
20
V
Voltage
I/O digital supply voltage (VIO_IN with respect to VIO_GND)
VBUS
–0.3
VIOmax +
0.3
VIOmax +
0.3
V
–2
20
V
Voltage on the GPADC pins: GPADC_IN0, GPADC_IN1
–0.3
5.25
V
Voltage on the GPADC pins: GPADC_IN2
–0.3
2.5
V
OTP supply voltage VPROG
–0.3
20
V
Voltage on VRTC digital input pins
Without fail-safe
With fail-safe
–0.3
2.15
V
–0.3
5.25
Voltage on VIO digital input pins (VIO_IN pin reference)
–0.3
VIOmax +
0.3
V
Voltage on VSYS digital input pins (VCC1 pin reference)
–0.3
6
V
Peak output current on all pins other than power resources
–5
5
mA
Current
Power pins, nFBGA
Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT total per phase
1
A
4
A
LDOs
1
A
Junction temperature range, TJ
Storage temperature, Tstg
–45
150
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) When operating the TPS659038-Q1 andTPS659039-Q1 devices without an external crystal, each SMPS regulating an output voltage
greater than 1.8 V must be disabled before VCC is removed. Lowering VCC below the programmed VSYS_LO level while any SMPS is
regulating an output voltage above 1.8 V may cause damage to the device.
5.2 ESD Ratings
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002(1)
Charge device model (CDM), per AEC Q100-011
Corner pins (A1, A13, N1, and N13)
All pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
VALUE
±2000
±750
±500
UNIT
V
V
18
Specifications
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