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ADR425BR(RevI) Ultraprecision, Low Noise, 2.048 V/2.500 V/3.00 V/5.00 V XFET Voltage References ADI
Analog Devices ADI
ADR425BR Datasheet PDF : 24 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ADR420/ADR421/ADR423/ADR425
THEORY OF OPERATION
The ADR42x series of references uses a reference generation
technique known as XFET (eXtra implanted junction FET).
This technique yields a reference with low supply current, good
thermal hysteresis, and exceptionally low noise. The core of the
XFET reference consists of two junction field-effect transistors
(JFET), one having an extra channel implant to raise its pinch-
off voltage. By running the two JFETs at the same drain current,
the difference in pinch-off voltage can be amplified and used to
form a highly stable voltage reference.
The intrinsic reference voltage is about 0.5 V with a negative
temperature coefficient of about −120 ppm/°C. This slope is
essentially constant to the dielectric constant of silicon and can
be closely compensated by adding a correction term generated
in the same fashion as the proportional-to-temperature (PTAT)
term used to compensate band gap references. The primary
advantage over a band gap reference is that the intrinsic tem-
perature coefficient is approximately 30 times lower (therefore
requiring less correction). This results in much lower noise
because most of the noise of a band gap reference comes from
the temperature compensation circuitry.
Figure 38 shows the basic topology of the ADR42x series. The
temperature correction term is provided by a current source
with a value designed to be proportional to absolute tempera-
ture. The general equation is
VOUT = G × (ΔVP R1 × IPTAT)
(1)
where:
G is the gain of the reciprocal of the divider ratio.
ΔVP is the difference in pinch-off voltage between the two JFETs.
IPTAT is the positive temperature coefficient correction current.
Each ADR42x device is created by on-chip adjustment of R2
and R3 to achieve the specified reference output.
I1
I1
IPTAT
VIN
ADR420/ADR421/
ADR423/ADR425
VOUT
R2
*
VP R1
R3
*EXTRA CHANNEL IMPLANT
VOUT = G(VP – R1 × IPTAT)
Figure 38. Simplified Schematic
GND
DEVICE POWER DISSIPATION CONSIDERATIONS
The ADR42x family of references is guaranteed to deliver load
currents to 10 mA with an input voltage that ranges from 4.5 V
to 18 V. When these devices are used in applications at higher
currents, the following equation should be used to account for
the temperature effects due to power dissipation increases:
TJ = PD × θJA + TA
(2)
where:
TJ and TA are the junction temperature and the ambient
temperature, respectively.
PD is the device power dissipation.
θJA is the device package thermal resistance.
BASIC VOLTAGE REFERENCE CONNECTIONS
Voltage references, in general, require a bypass capacitor
connected from VOUT to GND. The circuit in Figure 39
illustrates the basic configuration for the ADR42x family of
references. Other than a 0.1 μF capacitor at the output to help
improve noise suppression, a large output capacitor at the
output is not required for circuit stability.
VIN
+
10µF 0.1µF
TP 1 ADR420/ 8 TP
2
ADR421/
ADR423/
7 NIC
NIC 3
ADR425
OUTPUT
6
TOP VIEW
4 (Not to Scale) 5 TRIM
0.1µF
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
Figure 39. Basic Voltage Reference Configuration
NOISE PERFORMANCE
The noise generated by ADR42x references is typically less
than 2 μV p-p over the 0.1 Hz to 10 Hz band for the ADR420,
ADR421, and ADR423. Figure 24 shows the 0.1 Hz to 10 Hz
noise of the ADR421, which is only 1.75 μV p-p. The noise
measurement is made with a band-pass filter made of a 2-pole
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
low-pass filter with a corner frequency at 10 Hz.
TURN-ON TIME
At power-up (cold start), the time required for the output
voltage to reach its final value within a specified error band
is defined as the turn-on settling time. Two components typi-
cally associated with this are the time for the active circuits to
settle and the time for the thermal gradients on the chip to
stabilize. Figure 31 to Figure 35 show the turn-on settling time
for the ADR421.
Rev. I | Page 16 of 24
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