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K04808BISQ View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
K04808BISQ Low-Noise Clock Jitter Cleaner with Dual Loop PLLs TI
Texas Instruments TI
K04808BISQ Datasheet PDF : 139 Pages
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LMK04803, LMK04805, LMK04806, LMK04808
SNAS489K – MARCH 2011 – REVISED DECEMBER 2014
Distribution
Path
SYNC
(SYNC_POL
_INV=1)
CLKout0
6 cycles
CLKoutX_Y_DDLY & CLKoutX_Y_HS
6 cycles
4.5
cycles
2.5 1 cycle
cycles
CLKout2
CLKout4
CLKout5
AB
C
D EF
CLKout0_1_DIV = 2, CLKout0_1_DDLY = 5
CLKout2_3_DIV = 4, CLKout2_3_DDLY = 7
CLKout4_5_DIV = 4, CLKout4_5_DDLY = 8
CLKout0_1_HS = 1
CLKout2_3_HS = 0
CLKout4_5_HS = 0
SYNC_QUAL = 0 (No qualification)
Figure 12. Clock Output Synchronization using the SYNC Pin (Active Low)
Figure 12 illustrates the timing with different digital delays programmed.
• Time A) SYNC assertion event is latched.
• Time B) SYNC unassertion latched.
• Time C) All outputs toggle and remain low. A glitch pulse can occur at this time as shown by CLKout2.
• Time D) After 6 + 4.5 = 10.5 cycles CLKout0 rises. This is the shortest time from SYNC unassertion
registration to clock rising edge possible.
• Time E) After 6 + 7 = 13 cycles CLKout2 rises. CLKout2 and CLKout4, 5 are programmed for quadrature
operation.
• Time F) After 6 + 8 = 14 cycles CLKout4 and 5 rise. Since CLKout4 and 5 are driven by the same clock
divider and delay circuit, their timing is always the same.
8.3.9.3.5 Dynamically Programming Digital Delay
To use dynamic digital delay synchronization qualification set SYNC_QUAL = 1. This causes the SYNC pulse to
be qualified by a clock output so that the SYNC event occurs after a specified time from a clock output transition.
This allows the relative adjustment of clock output phase in real-time with no or minimum interruption of clock
outputs. Hence the term "dynamic digital delay".
Note that changing the phase of a clock output requires momentarily altering in the rate of change of the clock
output phase and therefore by definition results in a frequency distortion of the signal.
Without qualifying the SYNC with an output clock, the newly synchronized clocks would have a random and
unknown digital delay (or phase) with respect to clock outputs not currently being synchronized.
Copyright © 2011–2014, Texas Instruments Incorporated
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