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LTC6948 View Datasheet(PDF) - Linear Technology

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LTC6948 Datasheet PDF : 36 Pages
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LTC6948
Operation
Charge Pump Functions
The charge pump contains additional features to aid in
system startup. See Table 7 below for a summary.
Table 7. Charge Pump Function Bit Descriptions
BIT
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPLE
Linearizer Enable
CPMID
Enable Mid-Voltage Bias
CPRST
Reset PFD
CPUP
Force Source Current
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0D enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge
pump sourcing current is disabled. Alternately, when
CPCLO is enabled and the CP pin voltage is less than
approximately 0.9V, the TLO status flag is set, and the
charge pump sinking current is disabled. See Figure 4 for
a simplified schematic.
The CPMID bit also found in register h0D enables a resis-
tive VCP+/2 output bias which may be used to pre-bias
troublesome loop filters into a valid voltage range. When
using CPMID, it is recommended to also assert the CPRST
bit, forcing a PFD reset. Both CPMID and CPRST must be
set to 0 for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a precharge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to 0 to
allow the loop to lock.
The CPWIDE bit extends the charge pump output current
pulse width by increasing the PFD reset path’s delay value
(see Figure 2). CPWIDE is normally set to 0.
Charge Pump Linearizer
When the LTC6948 is operated in fractional mode, the
charge pump’s current output versus its phase stimulus
(its gain linearity) must be extremely accurate. The CP
gain linearizer automatically adds a correction current ILIN
to minimize the charge pump’s impact on in-band phase
noise and spurious products during fractional operation.
The CP gain linearizer is enabled by setting CPLE = 1. It is
automatically disabled when in integer mode. CPLE should
be set to 0 if CPRST or CPMID are asserted to prevent the
linearizer from producing unintended currents.
VCO
The integrated VCO is available in one of four frequency
ranges. The output frequency range may be further ex-
tended by utilizing the output divider (see Available Options
table, for more details). The wide frequency range of the
VCO, coupled with the output divider capability, allows the
LTC6948 to cover an extremely wide range of continuously
selectable frequencies.
The BB and TB pins are used to bias internal VCO cir-
cuitry. The BB pin has a 2k output resistance and should
be bypassed with a 1µF ceramic capacitor to GND, giving
a time constant of 2ms. The TB pin has a 2.5k output
resistance and should be bypassed with a 2.2µF ceramic
capacitor to GND, resulting in a time constant of 5.5ms.
Stable bias voltages are achieved after approximately 3
time constants following power-up.
VCO Calibration
The VCO must be calibrated each time its frequency is
changed by changing any of fREF, the R divider value, the
N divider value, or Δ∑ modulator fractional value, but not
the O divider (see the Applications Information section
For more information www.linear.com/LTC6948
6948f
17
 

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