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LTC6948 View Datasheet(PDF) - Linear Technology

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LTC6948 Datasheet PDF : 36 Pages
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LTC6948
Operation
ment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 2 for a simplified schematic
of the PFD.
D
Q
UP
R DIV
RST
CPRST
DELAY
N DIV
D
Q
RST
DOWN
6948 F02
Figure 2. Simplified PFD Schematic
Lock Indicator
The lock indicator uses internal signals from the PFD to
measure phase coincidence between the R and N divider
output signals. It is enabled by programming LKCT[1:0]
in the serial port register h0C (see Table 5), and produces
both LOCK and UNLOCK status flags, available through
both the STAT output and serial port register h00.
The user sets the phase difference lock window time tLWW
for a valid LOCK condition with the LKWIN[2:0] bits. When
using the device as a fractional-N synthesizer (fractional
mode), the Δ∑ modulator changes the instantaneous phase
seen at the PFD on every R_DIV and N_DIV cycle. The
maximum allowable time difference in this case depends
upon both the VCO frequency fVCO and also the charge
pump linearization enable bit CPLE (see the Charge Pump
Linearizer section for an explanation of this function). Table
3 contains recommended settings for LKWIN[2:0] when
using the device in fractional mode. See the Applications
Information section for examples.
Table 3. LKWIN[2:0] Fractional Mode Programming
LKWIN[2:0]
0
tLWW
5.0ns
fVCO (CPLE = 1)
≥2.97GHz
fVCO (CPLE = 0)
≥1.35GHz
1
7.35ns
≥2.00GHz
≥919MHz
2
10.7ns
≥1.39GHz
≥632MHz
3
15.8ns
≥941MHz
≥428MHz
4
23.0ns
≥646MHz
≥294MHz
5
34.5ns
≥431MHz
≥196MHz
6
50.5ns
≥294MHz
≥134MHz
7
76.0ns
≥196MHz
≥89MHz
When using the device as an integer-N synthesizer (integer
mode), the phase difference seen at the PFD is minimized
by the feedback of the PLL and no longer depends upon
fVCO. Table 4 contains recommended settings for different
fPFD frequencies. See the Applications Information section
for examples.
Table 4. LKWIN[2:0] Integer Mode Programming
LKWIN[2:0]
0
tLWW
5.0ns
fPFD
>6.8MHz
1
7.35ns
≤6.8MHz
2
10.7ns
≤4.7MHz
3
15.8ns
≤3.2MHz
4
23.0ns
≤2.2MHz
5
34.5ns
≤1.5MHz
6
50.5ns
≤1.0MHz
7
76.0ns
≤660kHz
The PFD phase difference must be less than tLWW for the
COUNTS number of successive counts before the lock
indicator asserts the LOCK flag. The LKCT[1:0] bits found
in register h0C are used to set COUNTS depending upon
the application. Set LKCT to 0 to disable the lock indicator.
See Table 5 for LKCT[1:0] programming and the Applica-
tions Information section for examples.
For more information www.linear.com/LTC6948
6948f
15
 

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