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BQ24153 Просмотр технического описания (PDF) - Texas Instruments

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BQ24153 Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support TI
Texas Instruments TI
BQ24153 Datasheet PDF : 41 Pages
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bq24153
bq24156, bq24158
SLUSA27 – MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
BAD ADAPTOR DETECTION
VIN(min)
Input voltage lower limit
Deglitch time for VBUS rising above
VIN(min)
Hysteresis for VIN(min)
ISHORT
Current source to GND
tINT
Detection Interval
INPUT BASED DYNAMIC POWER MANAGEMENT
BAD ADAPTOR DETECTION
Rising voltage, 2-mV overdrive, tRISE = 100 ns
Input voltage rising
During bad adaptor detection
Input power source detection
3.6
3.8
4.0
V
30
ms
100
200 mV
20
30
40 mA
2
S
VIN_DPM
Input Voltage DPM threshold programmable
range
4.2
4.76
V
VIN DPM threshold accuracy
–3%
1%
INPUT CURRENT LIMITING
IIN_LIMIT
Input current limiting threshold
VREF BIAS REGULATOR
IIN = 100 mA
IIN = 500 mA
TJ = 0°C – 125°C
TJ = –40°C –125°C
TJ = 0°C – 125°C
TJ = –40°C –125°C
88
93
98 mA
86
93
98
450
475
500 mA
440
475
500
VREF
Internal bias regulator voltage
VREF output short current limit
BATTERY RECHARGE THRESHOLD
VBUS >VIN(min) or V(CSOUT) > V(BATMIN),
I(VREF) = 1 mA, C(VREF) = 1 mF
2
6.5
V
30
mA
V(RCH)
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
Below V(OREG)
V(SCOUT) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
100
120
150 mV
130
ms
VOL(STAT)
Low-level output saturation voltage, STAT
pin
High-level leakage current for STAT
IO = 10 mA, sink current
Voltage on STAT pin is 5 V
0.55
V
1 mA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(BIAS)
Input bias current
f(SCL)
SCL clock frequency
BATTERY DETECTION
IO = 10 mA, sink current
V(pull-up) = 1.8 V, SDA and SCL
V(pull-up) = 1.8 V, SDA and SCL
V(pull-up) = 1.8 V, SDA and SCL
0.4
V
0.4
V
1.2
V
1 mA
3.4 MHz
I(DETECT)
Battery detection current before charge
done (sink current) (1)
tDETECT
Battery detection time
SLEEP COMPARATOR
Begins after termination detected,
VCSOUT V(OREG)
–0.5
mA
262
ms
V(SLP)
Sleep-mode entry threshold,
VBUS – VCSOUT
V(SLP_EXIT)
Sleep-mode exit hysteresis
Deglitch time for VBUS rising above V(SLP) +
V(SLP_EXIT)
UNDERVOLTAGE LOCKOUT (UVLO)
2.3 V V(CSOUT) V(OREG), VBUS falling
2.3 V V(CSOUT) V(OREG)
Rising voltage, 2-mV overdrive, tRISE = 100 ns
0
40
100 mV
140
200
260 mV
30
ms
VUVLO
VUVLO(HYS)
IC active threshold voltage
IC active hysteresis
VBUS rising - Exits UVLO
VBUS falling below VUVLO - Enters UVLO
3.05
3.3 3.55
V
120
150
mV
(1) Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low.
6
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