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BQ24153 Просмотр технического описания (PDF) - Texas Instruments

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BQ24153 Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support TI
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BQ24153 Datasheet PDF : 41 Pages
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bq24153
bq24156, bq24158
SLUSA27 – MARCH 2010
www.ti.com
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
START
Condition
1
2
8
Figure 32. Acknowledge on the I2C Bus™
9
Clock Pulse for
Acknowledgement
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPEATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
ACK
Clock Line Held Low While
Interrupts are Serviced
Figure 33. Bus Protocol
Sr
ACK
or
P
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
26
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