SLUSA27 – MARCH 2010
Figure 32. Acknowledge on the I2C Bus™
Clock Pulse for
Recognize START or
Signal From Slave
Recognize STOP or
Clock Line Held Low While
Interrupts are Serviced
Figure 33. Bus Protocol
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
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