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BQ24153 Просмотр технического описания (PDF) - Texas Instruments

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BQ24153 Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support TI
Texas Instruments TI
BQ24153 Datasheet PDF : 41 Pages
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bq24153
bq24156, bq24158
SLUSA27 – MARCH 2010
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that
SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as HS-mode. The bq24150/1 device supports 7-bit addressing only. The device 7-bit address is defined as
‘1101011’ (6BH) for bq24153, and ‘1101010’ (6AH) for bq24156/8.
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 30. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 30. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 31). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 31) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 31. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 33). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Copyright © 2010, Texas Instruments Incorporated
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