SLUSA27 – MARCH 2010
OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if
HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in
Table 2. Operation Mode Summary
Charge (no fault)
Charge configure (fault, Vbus > VUVLO)
High impedance (Vbus < VUVLO)
Boost (no faults)
Any fault go to charge configure mode
Control Pins in Charge Mode
CD Pin (Charge Disable)
The CD pin is used to disabled the charging process. When CD=0, charge is enabled. When CD=1, charge is
disabled and VBUS pin is high impedance to GND. In 15-minute mode, setting CD=1 resets the 15-minute timer;
while in 32s mode, setting CD=1does NOT reset the 32-second timer.
SLRST Pin (Safety Limit Register 06H Reset, bq24156 only)
When SLRST=0, bq24156 will reset all the safety limits to default values, regardless of the write actions to safety
limits registers (06H). When SLRST=1, bq24156 can program the safety limit register until any write action to
other registers locks the programmed safety limits.
Boost Mode Operation (bq24153/8 only)
In 32 second mode, when OTG pin is in active status or the bit of operation mode (OPA_MODE) at control
register is set to 1, bq24153/8 operates in boost mode and delivers the power to VBUS from the battery. In
normal boost mode, bq24153/8 converts the battery voltage to VBUS-B (about 5.05V) and delivers a current as
much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector.
PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency
voltage-mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally
compensated using a Type-III compensation scheme that provides enough phase margin for stable operation
with a wide load range and battery voltage range.
In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle
current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is
set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.
Boost Start Up
To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start
PFM Mode at Light Load
In boost mode, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the
converter efficiency at light load condition. During boosting, the PWM converter is turned off once the inductor
current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to about
99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM
and PFM mode.
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Product Folder Link(s): bq24153 bq24156 bq24158