SLUSA27 – MARCH 2010
PWM Controller in Charge Mode
The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or
voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation
network used for both continuous and discontinuous current conduction operation. The voltage and current loops
are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable
operation, allowing the use of small ceramic capacitors with very low ESR. The device operates between 0% to
99.5% duty cycles.
The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side.The
input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET
(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap
circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal
2.4-A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate
in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel
FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used
when the current of the low-side FET is greater than 100mA to minimize power losses.
Battery Charging Process
At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit
current, I(SHORT), to the battery.
When the battery voltage is above VSHORT and below VOREG, the charge current ramps up to fast charge current,
IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT. The slew rate for fast charge
current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit,
IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery voltage reaches the
regulation voltage, VOREG, the charge current is tapered down as shown in Figure 26. The voltage regulation
feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. The regulation
voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface.
The IC monitors the charging current during the voltage regulation phase. When the termination is enabled, once
the termination threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the IC
terminates charge. The termination current level is programmable. To disable the charge current termination, the
host can set the charge termination bit (I_Term) of charge control register to 0, refer to I2C section for detail.
A new charge cycle is initiated when one of the following conditions is detected:
• The battery voltage falls below the V(OREG) – V(RCH) threshold.
• VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold.
• CE bit toggle or RESET bit is set (Host controlled)
Safety Timer in Charge Mode
At the beginning of charging process, the IC starts a 15-minute timer (T15min) that can be disable by any
write-action performed by host through I2C interface. Once the 15-minute timer is disabled, a 32-second timer
(T32sec) is automatically started. The 32-second timer can be reset by host using I2C interface. Writing “1” to
reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is automatically set to “0”
after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge
parameters are reset to default values. Then the 15-minute timer starts and the charge resumes.
During normal charging process, the IC is usually in 32-second mode with host control and 15-minute mode
without host control using I2C interface. The above process repeats until the battery is fully charged. If the
15-minute timer expires, the IC turns off the charge, enunciates FAULT on the STATx bits of status register, and
sends the 128ms interrupt pulse. This function prevents battery over charge if the host fails to reset the safety
timer. The 15-minute charge, with default parameters, allows time for a discharged battery to charge sufficiently
to be able to power the host and start communication. The safety timer flow chart is shown in Figure 27. Fault
condition is cleared by POR and fault status bits can only be updated after the status bits are read by the host.
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