ML4821CS View Datasheet(PDF) - Fairchild Semiconductor
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ML4821CS Datasheet PDF : 12 Pages
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PRODUCT SPECIFICATION
ML4821
INV
7
+8V
S.S
9
–
+
VREF
+8V
6.2kΩ
EA OUT
6
Figure 3. Error and Current Amplifier Configuration
100
0
VCC = 15V
80
GAIN
VO = 1.0V TO 5.0V
RL = 100kΩ
–30
TA= 25°C
60
60
40
90
PHASE
20
120
0
150
–20
180
10
100
1.0k
10k
100k 1.0M
10M
f, FREQUENCY (Hz)
Figure 4. Error Amplifier Open-loop Gain and
Phase vs. Frequency.
0
VCC
SOURCE
SATURATION
VCC = 15V
.0
TA = 25°C
80µs PULSED
LOAD
2.0
TA = –55°C
3.0
2.0
.0
0
0
TA = –55°C
SINK
SATURATION
TA = 25°C
GND
200
400
600
800
IO, OUTPUT LOAD CURRENT (mA)
Figure 5. Output Saturation Voltage vs. Output Current.
The output of the gain modulator is a current which appears
on IA+ to form the reference for the current error amplifier
and is given as:
IGM = K × ISINE × (VEA – 0.8)
where:
ISINE is the current in the dropping resistor, VEA is the
output of the error amplifier and K is a constant deter-
mined by the VRMS input.
IGM(MAX) = 2-R---.--5T-
The output current of the gain modulator is limited to:
This sets the system current limit.The multiplier output
current is converted into the reference voltage for the current
(IA) amplifier through a resistor to ground on IA+.
0.5
OPERATING BOUNDRY
0.4
0.3
K
DESIGN
FOR
BROWNOUT
0.2
0.23
0.1
DESIGN
FOR
NORMAL
OPERATIONS
THIS IS THE MINIMUM
OPERATING
VOLTAGE POINT
THIS GAIN CURVE TAKES
OUT THE 1/(VIN)2
DEPENDENCY OF THE
VOLTAGE CONTROL LOOP
0
0
1
2
3
4
5
6
7
85VAC 120VAC
220VAC
VRMS
Figure 6. K-factor. Gain Modulator gain with respect to
the voltage at VRMS.
Figure 6 shows the gain adjustor (K) with respect to the
voltage at VRMS. The curve has been separated in two parts.
The right hand part is for operation under normal conditions
in the voltage range from minimum line voltage to maximum
line voltage (90VAC to 260VAC). 85VAC on the curve has
been chosen to account for tolerances. Under normal operat-
ing conditions as input voltage decreases the gain increases
compensating for the drop in the loop gain.
Under brownout conditions (below 85VAC) the gain
decreases to limit the amount of current that is drawn from
the line thus preventing an overload condition. This is a very
useful feature since in many cases the load for a PFC is a
constant power load. The input current has to go high to
compensate for a drop in the input voltage.
REV. 1.0.2 6/19/01
7
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