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DRV8308 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DRV8308 Brushless DC Motor Controller TI
Texas Instruments TI
DRV8308 Datasheet PDF : 59 Pages
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DRV8308
SLVSCF7B – FEBRUARY 2014 – REVISED NOVEMBER 2017
www.ti.com
Pin Functions (continued)
NAME
PIN
NO.
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
ENABLE
Enables and disables motor. Polarity is
22
I programmable. Internal pulldown
resistor.
FAULTn
Fault indicator – active low when
17
OD overcurrent, or overtemperature. Open-
drain output.
FGOUT
Outputs a TACH signal generated from
16
OD the FG amplifier or Hall sensors.
Open-drain output.
LOCKn
Outputs a signal that indicates the
18
OD speed loop is locked. Open-drain
output.
RESET
23
I
Active high to reset all internal logic.
Internal pulldown resistor.
SERIAL INTERFACE
SCLK (2)
11
I/OD Serial clock
SPI mode: Serial clock input. Data is clocked on rising edges.
Internal pulldown resistor.
EEPROM mode: Connect to EEPROM CLK. Open-drain
output requires external pullup.
SCS (2)
12
I/OD Serial chip select
SPI mode: Active high enables serial interface operation.
Internal pulldown resistor.
EEPROM mode: Connect to EEPROM CS. Open-drain output
requires external pullup.
SDATAI
14
I Serial data input
SPI mode: Serial data input. Internal pulldown resistor.
EEPROM mode: Serial data input. Connect to EEPROM DO
terminal.
SDATAO
15
OD Serial data output
SPI mode: Serial data output. Open-drain output.
EEPROM mode: Connect to EEPROM DI. Open-drain output
requires external pullup.
SMODE
13
I Serial mode
SPI mode: leave open or connect to ground for SPI interface
mode.
EEPROM mode: Connect to logic high to for EEPROM mode.
POWER STAGE INTERFACE
ISEN
31
I Low-side current sense resistor
Connect to low-side current sense resistor
U
33
I
V
36
I
Measures motor phase voltages for
VFETOCP
Connect to motor windings
W
39
I
UHSG
32
O
VHSG
35
O High-side FET gate outputs
Connect to high-side 1/2-H N-channel FET gate
WHSG
38
O
ULSG
34
O
VLSG
37
O Low-side FET gate outputs
Connect to low-side 1/2-H N-channel FET gate
WLSG
40
O
HALL AND FG INTERFACE
FGFB
8
O FG amplifier feedback pin
Connect feedback network to FGIN–
FGINN_TACH
9
I (3)
FG amplifier negative input or TACH
input
Connect to FG trace and filter components. When using a
TACH with FGSEL= 3, connect a logic-level TACH signal. If
unused, connect FGFB to FG–.
FGINP
10
I/O FG amplifier positive input
Connect to FG trace and filter components on the PCB (if
used).
(2) In SPI mode, these pins are inputs; in EEPROM mode, they are open-drain outputs.
(3) When using FG amplifier, this pin is an analog input. If in TACH mode, this is a logic-level input.
4
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