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DRV8308
SLVSCF7B – FEBRUARY 2014 – REVISED NOVEMBER 2017
Device Functional Modes (continued)
The output of the integrator is applied to a programmable digital filter. The filter has one pole and one zero. The
pole location is programmable from approximately 100 to 1600 Hz, and is set via the FILK1 register; the zero
location is programmable from 2 to 100 Hz and is set via the FILK2 register. The filter may be bypassed by
setting the BYPFILT bit.
For a given pole and zero frequency, FILK1 and FILK2 are calculated as follows:
FILK2
2S fz
219
fs ,
1 S fz
fs
FILK1
2S fp
216
fs
1 S fp
fs
where
• fz is the desired zero frequency
• fp is the desired pole frequency
• fs is the filter sample rate (195000 Hz)
• The result is rounded to the nearest integer
(1)
Following the filter is a programmable lead compensator, which also contains one pole and one zero. The
compensator characteristics are programmable by the COMPK1 and COMPK2 registers. Center frequency is
programmable between 20 and 100 Hz, with a phase lead between 0° and 80°. The compensator may be
bypassed by setting the BYPCOMP bit.
For a given pole and zero frequency, COMPK1 and COMPK2 are calculated as follows:
COMPK2
2S fz
219
fs ,
1 S fz
fs
COMPK1
2S fp
216
fs
1 S fp
fs
where
• fz is the desired zero frequency
• fp is the desired pole frequency
• fs is the filter sample rate (195000 Hz)
• The result is rounded to the nearest integer
(2)
The filter and compensator ratios also scale DC gain in the same way as LOOPGAIN. DC gain is scaled by
2×(FILK2/FILK1) and 0.5×(COMPK2/COMPK1).
The digital filter and compensator are reset to 0 whenever the motor is disabled.
The integrator, filter, and lead compensator result in a typical open-loop response as shown in Figure 18. Note
that the locations of the poles and zeros are not restricted to what is shown.
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