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Part NameDescriptionManufacturer
DRV8308 Brushless DC Motor Controller TI
Texas Instruments TI
DRV8308 Datasheet PDF : 59 Pages
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DRV8308
SLVSCF7B – FEBRUARY 2014 – REVISED NOVEMBER 2017
tDRIVE
HS drive
xHS
High Z
Low
Z
High Z Low Z
LS drive
xLS
High Z
High Z
www.ti.com
Low Z
High Z
tDRIVE
High Z
Low
Z
tDEAD
Figure 15. Drive Timing
tDEAD
The peak drive current of the pre-drivers is adjustable by setting the IDRIVE register bits. Peak drive currents
may be set between 10 and 130 mA. Adjusting the peak current changes the output slew rate, which also
depends on the FET input capacitance and gate charge.
When changing the state of the output, the peak current is applied for a short period of time (tDRIVE), to charge
the gate capacitance. This time is selected by setting the TDRIVE register bits. Times of 1, 5, 10, or 15 µs may
be selected. After this time, a weak current source is used to keep the gate at the desired state. When selecting
the gate drive strength for a given external FET, the selected current must be high enough to fully charge and
discharge the gate during the time when driven at full current, or excessive power is dissipated in the FET.
During high-side turn-on, the low-side gate is held low with a low impedance. This prevents the gate-source
capacitance of the low-side FET from inducing turn-on. Similarly, during low-side turn-on, the high-side gate is
held off with a low impedance.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. Additional dead time can be added (in digital logic) by setting
the DTIME register bits.
7.3.9 Current Limit
The current limit circuit activates if the voltage detected across the low-side sense resistor exceeds VLIMITER. This
feature restricts motor current to less than VLIMITER/RISENSE, and it reduces the requirements of the external power
supply. Note that the current limit circuit is ignored immediately after the PWM signal goes active for a short
blanking time, to prevent false trips of the current limit circuit.
If current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle. If synchronous
rectification is enabled when the current limit activates, the low-side FET is activated while the high-side FET is
disabled.
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