STA339BWTR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

View to exact match

STA339BWTR

2.1-channel high-efficiency digital audio system / PowerSSO-36 slug down Package

STMicroelectronics 

Register description

STA339BW

7.6.7

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

External amplifier power down

Bit R/W

7

R/W

Table 52. External amplifier power down

RST

Name

Description

0

EAPD

0: External power stage power down active

1: Normal operation

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

register also controls the FFX4B/EAPD output pin when OCFG = 10.

7.7

7.7.1

7.7.2

7.7.3

Volume control registers (addr 0x06 - 0x0A)

Mute/line output configuration register

D7

LOC1

0

D6

LOC0

0

D5

D4

Reserved

0

0

D3

C3M

0

D2

C2M

0

D1

C1M

0

LOC[1:0]

Table 53. Line output configuration

Line output configuration

00

Line output fixed - no volume, no EQ

01

Line output variable - CH3 volume effects line output, no EQ

10

Line output variable with EQ - CH3 volume effects line output

D0

MMUTE

0

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

Master volume register

D7

MV7

1

D6

MV6

1

D5

MV5

1

D4

MV4

1

D3

MV3

1

D2

MV2

1

D1

MV1

1

D0

MV0

1

Channel 1 volume

D7

C1V7

0

D6

C1V6

1

D5

C1V5

1

D4

C1V4

0

D3

C1V3

0

D2

C1V2

0

D1

C1V1

0

D0

C1V0

0

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