S25FL128P View Datasheet(PDF) - Spansion Inc.

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S25FL128P

128 Megabit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Bus

Spansion Inc. 

Data Sheet

11. Command Definitions

The host system must shift all commands, addresses, and data in and out of the device, beginning with the

most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte

command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on

the rising edge of SCK. Table 11.6 on page 38 lists the complete set of commands.

Every command sequence begins with a one-byte command code. The command may be followed by

address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the

command sequence has been written.

The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed

(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence

on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.

The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable

(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise

the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high

when the number of clock pulses after CS# is driven low is an exact multiple of eight.

The device ignores any attempt to access the memory array during a Write Status Register, program, or

erase operation, and continues the operation uninterrupted.

11.1 Read Data Bytes (READ: 03h)

11.1.1

Serial Mode

The Read Data Bytes (READ-Serial Mode) command reads data from the memory array at the frequency

(fSCK) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the

device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0).

Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on

SO at a frequency fSCK, on the falling edge of SCK.

Figure 11.1 and Table 11.6 detail the READ command sequence. The first byte specified can be at any

location. The device automatically increments to the next higher address after each byte of data is output.

The entire memory array can therefore be read with a single READ command. When the highest address is

reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

The READ command is terminated by driving CS# high at any time during data output. The device rejects any

READ command issued while it is executing a program, erase, or Write Status Register operation, and

continues the operation uninterrupted.

Figure 11.1 Read Data Bytes (READ) Command Sequence

CS#

Mode 3

SCK Mode 0

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Command

24-Bit Address

SI

SO

Hi-Z

23 22 21

MSB

32 10

Data Out 1

Data Out 2

7 6 5 4 3 2 107

MSB

September 21, 2012 S25FL128P_00_11

S25FL128P

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