Philips Semiconductors
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
Product specification
74ALVCH162601
FEATURES
• Complies with JEDEC standard
no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTE™ flow-through
standard pin-out architecture
• Low inductance multiple VCC and
ground pins for minimum noise and
ground bounce
• All data inputs have bus hold
circuitry
• Integrated 30 Ω termination
resistors.
DESCRIPTION
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OEAB and OEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
To ensure the high-impedance state during power-down, OEBA and OEAB
should be tied to VCC through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
propagation delay An, Bn to Bn, An
CI/O
input/output capacitance
CI
input capacitance
CPD
power dissipation capacitance per
latch
CONDITIONS
CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
TYPICAL
4.0
3.1
8.0
4.0
UNIT
ns
ns
pF
pF
21
pF
3
pF
1999 Oct 14
2