ISL6205CB-T View Datasheet(PDF) - Intersil
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ISL6205CB-T Datasheet PDF : 6 Pages
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ISL6205
Three-State PWM Input
A unique feature of the ISL6205 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the Electrical Specifications determine
when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 0.5V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 3V, the LGATE is
allowed to rise. PHASE continues to be monitored during the
lower gate rise time. If PHASE has not dropped below 3V
within 250ns of the falling edge of the PWM input, LGATE is
taken high to keep the bootstrap capacitor charged. If the
PHASE voltage exceeds the 3V threshold during this period
and remains high for longer than 2µs, the LGATE transitions
low. Both upper and lower gates are then held low until the
next rising edge of the PWM signal.
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
9.1V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Bootstrap Diode and Capacitor
An external bootstrap diode and a bootstrap capacitor are
required for the bootstrap circuit. The connection is shown in
the typical application schematic. Typically a schottky diode
should be employed for its low forward drop. Its voltage
rating must be greater than the maximum battery voltage
plus 5V.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
CBOOT ≥ ∆---Q--V---G-B---A-O---T-O--E---T-
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a MOSFET is chosen as the upper
MOSFET. Its gate charge, QGATE , from the data sheet is
30nC for a 5V upper gate drive. We will assume a 200mV
droop in drive voltage over the PWM cycle. We find that a
bootstrap capacitance of at least 0.15µF is required. The
next larger standard value capacitance is 0.22µF. A good
quality ceramic capacitor is recommended.
Gate Driver Voltage
The ISL6205 provides the user flexibility in choosing the
lower gate drive voltage. Simply applying a voltage from 5V
up to 12V on PVCC will set the lower driver rail voltage. The
upper gate driver rail voltage is set independently by
connecting a 5V supply to the anode of the bootstrap diode,
as shown in Figure 1.
+12V
+5V
VBAT
BOOT
PVCC
VCC
PWM DRIVE
ISL6205
UGATE
PHASE
LGATE
FIGURE 1. APPLICATION CIRCUIT TO USE 12V LOWER GATE
VOLTAGE AND 5V UPPER GATE VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125oC. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
P = fsw(VUQU + VLQL) + IDDQVCC
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically 30mW.
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