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ISL6205CB View Datasheet(PDF) - Intersil

Part Name
Description
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ISL6205CB Datasheet PDF : 6 Pages
1 2 3 4 5 6
ISL6205
Functional Pin Description
UGATE (Pin 1)
Upper gate drive output. Connect to the gate of high-side
power N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin and a schottky diode between this pin and a 5V
supply. The bootstrap capacitor provides the charge to turn
on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The
PWM signal can enter three distinct states during
operation. See the three-state PWM Input section under
DESCRIPTION for further details. Connect this pin to the
PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
PVCC (Pin 7)
This pin supplies the lower gate drive bias. Connect this pin
to either +12V or +5V.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
Description
Operation
Designed for versatility and speed, the ISL6205 dual
MOSFET driver controls both high-side and low-side
N-Channel FETs from one externally provided PWM signal.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [tPDLLGATE], the
lower gate begins to fall. Typical fall times [tFLGATE] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [tPDHUGATE] based
on how quickly the LGATE voltage drops below 0.5V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[tRUGATE] and the upper MOSFET turns on.
Timing Diagram
PWM
tPDHUGATE
UGATE
LGATE
tPDLLGATE
tFLGATE
tRUGATE
tPDLUGATE
tFUGATE
tPDHLGATE
tRLGATE
4
 

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