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ISL26311 View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL26311 12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels Intersil
Intersil Intersil
ISL26311 Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance
at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN
MAX
(Note 6)
TYP
(Note 6)
UNITS
PSRR Power Supply Rejection Ratio
70
dB
DYNAMIC PERFORMANCE
SNR
Signal-to-Noise
Notes: VIN = FS-0.1dB, fIN = 10kHz
Differential Inputs
Single-Ended Inputs
73.4
dB
73.4
dB
SINAD
Signal-to-Noise + Distortion
Notes: VIN = FS-0.1dB, fIN = 10kHz
Differential Inputs
Single-Ended Inputs
73.1
dB
73.1
dB
Total Harmonic Distortion
THD Notes: VIN = FS-0.1dB, fIN = 10kHz
Differential Inputs
Single-Ended Inputs
-86
dB
-86
dB
SFDR
BW
Spurious-free Dynamic Range
Notes: VIN = FS-0.1dB
-3dB Input Bandwidth
fIN = 20kHz
96
dB
2.5
MHz
tAD Sampling Aperture Delay
tjit Sampling Aperture Jitter
POWER SUPPLY REQUIREMENTS
12
ns
25
ps
VDD Supply Voltage
IDD Supply Current
PD Power Consumption
Normal Operation
2.7
5.25
V
2.2
3
mA
11
15
mW
IPD Power-down Current
Auto Power-Down Mode
8
50
µA
Istby Standby Mode Current
Auto Sleep Mode
0.4
mA
DIGITAL INPUTS
VIH
VIL
VOH
VOL
IIH, IIL
IOH = -1mA
IOL = 1mA
Input Leakage Current
Serial Clock Frequency
0.7 VDD
VDD-0.4
-100
V
0.2 VDD
V
V
0.2 VDD
V
100
nA
20
MHz
TIMING SPECIFICATIONS (Note 7)
tSCLK
tSCLK
tDATA
SCLK Period (in RAC Mode)
SCLK Period (in RSC, RDC Modes)
Safe Data Transfer Time After Conversion
State Begins
50
ns
50
200
ns
3.2
µs
tCSB_SCLK CSB Falling Low to SCLK Rising Edge
tSDI_SU SDI Setup Time with Respect to Positive
Edge of SCLK
40
ns
10
ns
tSDI_H SDI Hold Time with Respect to Positive
Edge of SCLK
10
ns
tSDO_V SDOUT Valid Time with Respect to
Negative Edge of SCLK
25
ns
tSDOZ_D SDOUT to High Impedance State After CNV Note 8
Rising Edge (or last SCLK falling edge)
85
ns
tACQ Acquisition Time when Fully Powered Up
tACQ Acquisition Time in Auto Sleep Mode
800
ns
2.1
µs
7
FN7549.1
July 3, 2012
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