ISL26323 View Datasheet(PDF) - Intersil

Part Name

Description

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ISL26323

12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels

Intersil 

ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

ADC STATE

Power-Up Idle

CNV

SCLK

tSCLK

Conversion N

Acquisition

tACQ

tSCLKH

Conversion

Idle

Conversion N+1

Acquisition

Conversion

tSDOZ_D

tCNV_SCLK

SDI

SDO

tSCLKL

D15 D14 . . . D5

D4

Configuration N+1

MSB MSB-1 . . . D1 LSB

Conversion Result N-1

Hi-Z State

D15 D14 . . . D5

D4

Configuration N+2

MSB MSB-1 . . .

tSDO_V

LSB

Conversion Result N

FIGURE 30. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE, WITHOUT EOC

Idle Acq.

tSDI_H

tSDI_SU

ADC STATE

Power-Up Idle Acquisition

tACQ

CNV

SCLK

Conversion N

Conversion

tDATA

tSCLK

tSCLKH

Conversion N+1

Idle Acquisition

Conversion

tCNV

tCNV_CLK

SDI

SDO

Hi-Z State

tSCLKL

D15 D14 . . . D5 D4

Configuration N+1

tSDI_H

tSDI_SU

D14 . . . D5 D4

Configuration N+2

MSB MSB-1 . . . D1 LSB

Conversion Result N-1

MSB MSB-1 . . . D1

Conversion Result N

FIGURE 31. TIMING DIAGRAM FOR READING DURING CONVERSION MODE, WITHOUT EOC

Idle

tSDO_V

ADC STATE

Power-Up Idle

CNV

Acquisition

Conversion N

Conversion

tCNV

tACQ

tSCLKH

SCLK

SDI

SDO

tSCLK

D15 D14

tSCLKL

D13 D12 . . .

Configuration N+1

MSB MSB-1

MSB-1 MSB-2 . . .

Conversion Result N-1

D4

Hi-Z State

D1 LSB

Idle Acquisition

Conversion N+1

Conversion

tDATA

tCNV_SCLK

D15

D14

D13

tSDI_H

D12

Configuration N+2

. . . D4

tSDI_SU

MSB MSB-1

MSB-1 MSB-2 . . . D1

tSDO_V

Conversion Result N

Idle

Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied).

FIGURE 32. TIMING DIAGRAM FOR READING SPANNING CONVERSION MODE, WITHOUT EOC

17

FN7549.1

July 3, 2012

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