FM24C256 View Datasheet(PDF) - Unspecified
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FM24C256 Datasheet PDF : 12 Pages
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FM24C256
By Master
Start
Address
S
Slave Address 1 A
No
Acknowledge
Data Byte
1P
Stop
By FM24C256
Acknowledge Data
Figure 7. Current Address Read
By Master
Start
Address
Acknowledge
No
Acknowledge
S
Slave Address 1 A
Data Byte
A
Data Byte
1P
By FM24C256
Acknowledge
Data
Figure 8. Sequential Read
Stop
Start
By Master
Address
Start
Address
S
Slave Address 0 A
By FM24C256
Address MSB
A
Address LSB
AS
Slave Address 1 A
Acknowledge
Figure 9. Selective (Random) Read
No
Acknowledge
Stop
Data Byte
1P
Data
Endurance
A FRAM internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read and write access. The FRAM
architecture is based on an array of rows and
columns. Rows (A14-A6) are subdivided into 8
segments (A5-A3). Each access causes an endurance
cycle for a row segment. In the FM24C256, there are
8 bytes per segment. Endurance can be optimized by
ensuring frequently accessed data is located in
different segments. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 30 accesses per second to
the same segment, 10 years time will elapse before
10 billion endurance cycles occur.
Rev 3.1
May 2005
Page 7 of 12
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