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FAN7930 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
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FAN7930
Fairchild
Fairchild Semiconductor Fairchild
FAN7930 Datasheet PDF : 22 Pages
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Applications Information
1. Startup: Normally, supply voltage (VCC) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding to detect zero current detection can be
used as a supply source. Once the supply voltage of the
PFC block exceeds 12V, internal operation is enabled
until the voltage drops to 8.5V. If VCC exceeds VZ, 20mA
current is sinking from VCC.
Figure 23. Circuit Around INV Pin
Figure 22. Startup Circuit
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, disable comparator, and output
UVLO comparator.
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of
OVP and disable function. The output current of the
amplifier changes according to the voltage difference of
the inverting and non-inverting input of the amplifier. To
cancel down the line input voltage effect on power factor
correction, effective control response of PFC block
should be slower than the line frequency and this
conflicts with the transient response of controller. Two-
pole one-zero type compensation may be used to meet
both requirements.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675V
and there is 0.175V hysteresis. The disable comparator
disables the operation when the voltage of the inverting
input is lower than 0.35V and there is 100mV hysteresis.
An external small-signal MOSFET can be used to
disable the IC, as shown in Figure 23. The IC operating
current decreases to reduce power consumption if the
IC is disabled. Figure 24 is the timing chart of the
internal circuit near the INV pin when rated PFC output
voltage is assumed at 390VDC and VCC supply voltage is
15V.
VOUTPFC
390Vdc
349V
70V
VINV
2.50V
2.24V
0.45V
VCC
15V
2.0V
IOUTCOMP
Disable
Current sourcing
413V
2.65V
390V
256V
55V
2.50V
1.64V
0.35V
I sinking
Current sourcing
VRDY
Voltage is decided by pull-up voltage.
OVP
Vcc<2V, internal logic is not alive.
- RDY pin is floating, so pull up voltage is shown.
- Internal signals are unknown.
t
Figure 24. Timing Chart for INV Block
3. RDY Output: When the INV voltage is higher than
2.24V, output UVLO voltage is triggered to high and
lasts until the INV voltage is lower than 1.64V. This
signal outputs through the RDY pin. RDY pin output is
open-drain type, so needs an external pull-up resistor to
supply the proper power source. The RDY pin output
remains floating until VCC is higher than 2V.
© 2010 Fairchild Semiconductor Corporation
FAN7930 • Rev. 1.0.1
11
www.fairchildsemi.com
 

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