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Q67100-Q1337 View Datasheet(PDF) - Siemens AG

Part Name
Description
View to exact match
Q67100-Q1337
Siemens
Siemens AG Siemens
Q67100-Q1337 Datasheet PDF : 22 Pages
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HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description (cont’d)
Pin
Type Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
VDD
Supply
VSS
VDDQ
Supply –
VSSQ
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Semiconductor Group
5
1998-10-01
 

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