Q67100-Q1337 View Datasheet(PDF) - Siemens AG

Part Name

Description

View to exact match

Q67100-Q1337

16Mbit Synchronous DRAM

Siemens AG 

HYB 39S16400/800/160AT-8/-10

16 MBit Synchronous DRAM

Notes

1. All voltages are referenced to VSS.

2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to

– 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50 % points with amplitude

measured peak to DC reference.

3. Under all conditions VDDQ must be less than or equal to VDD.

4. The value of VREF may be selected by the user to provide optimum noise margin in the system.

VREF has to be in the range between 0.43 × VDDQ and 0.47 × VDDQ and is expected to track

variations in VDDQ.

5. VIH may overshoot to VDD, VDDQ + 1.2 V for pulse width < 5 ns and VIL may undershoot to VSS,

VSSQ – 1.2 V for pulse width < 5 ns.

6. The specified values are valid when addresses are changed no more than three times during

tRC(MIN.) and when No Operation commands are registered on every rising clock edge during

tRC(MIN.).

7. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.).

8. An initial pause of 200 µs is required after power-up, then a Precharge All Banks command

must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set

Operation can begin.

9. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced

to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC

measurements assume tT = 1 ns with the AC output load circuit shown in figure below.

10. If clock rising time is longer than 1 ns, (tT/2 – 0.5) ns has to be added to this parameter.

11. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.

12. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to “wake-up” the device.

13. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

14. Referenced to the time which the output achieves the open circuit condition, not to output

voltage levels.

Semiconductor Group

18

1998-10-01

Share Link: