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M93C06-BN3 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M93C06-BN3 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
M93C06-BN3 Datasheet PDF : 30 Pages
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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 8. Write Sequence with One Clock Glitch
S
C
D
START
"0"
"1"
WRITE
An
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the master (the microcontrol-
ler). This can lead to a misalignment of the instruc-
tion of one or more bits (as shown in Figure 8) and
may lead to the writing of erroneous data at an er-
roneous address.
To combat this problem, the M93Cx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Cx6
family, are summarized in Table 4 to Table 6. For
example, a Write Data to Memory (WRITE) in-
struction on the M93C56 (or M93C66) expects 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
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