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YDA135 View Datasheet(PDF) - Yamaha Corporation

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Description
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YDA135 Datasheet PDF : 22 Pages
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YDA135
Description of terminal function
In the following explanations, "L" level and "H" level of SLEEP and MUTE terminals mean "VIL" and "VIH"
respectively, and "L" level and "H" level of PROT terminal mean "VOL" and "VOH" respectively.
"L" level and "H" level of output terminals such as HP_L and HN_L terminals also mean "VHOL" and "VHOH"
respectively.
Power supply and ground terminals
VDDL, VSSL, VDDR, VSSR (Pin No.48, 3, 13, 10)
VDDL and VSSL terminals are 5.0V power supply terminal and ground terminal for left channel signal processing
circuit respectively. VDDR and VSSR terminals are 5.0V power supply terminal and ground terminal for right
channel signal processing circuit respectively.
Left and right channels are equipped independent power supply terminal and ground terminal, respectirely.
All the ground terminals are connected through IC board (low resistor), but the power supply terminals for left and
right channels are separated from each other.
PVDDL, PVSSL, PVDDR, PVSSR (Pin No.38, 36, 23, 25)
PVDDL and PVSSL are 12 V power supply and ground terminals for left channel Power MOSFET driving circuit
respectively.
PVDDR and PVSSR are 12 V power supply and ground terminals for right channel Power MOSFET driving circuit
respectively.
Left and right channels are equipped independent power supply terminal and ground terminal, respectirely.
All the ground terminals are connected through IC board (low resistor), but the power supply terminals for left and
right channels are separated from each other.
Analog terminals
INL, NFINL, INR, NFINR (Pin No.47, 46, 14, 15)
INL and NFINL are analog signal input and gain adjustment terminals for left channel.
INR and NFINR are analog signal input and gain adjustment terminals for right channel.
The terminals are connected respectively to the negative input terminal and output terminal of the first stage
inversion operational amplifiers.
The amplifier gain is set by connecting an input resistor and a feedback resistor to both terminals as shown the
"Example of application circuit".
The use of this inversion operational amplifier allows making a filter such as low band boost filter.
VREFL, VREFR (Pin No.2, 11)
VREFL is the reference voltage output terminal for the left channel. It outputs 1/2 of 5V power supply terminal
(VDDL) voltage.
VREFR is the reference voltage output terminal for the right channel. It outputs 1/2 of 5V power supply terminal
(VDDR) voltage.
Connect a capacitor with capacitance necessary to stabilize the voltage. Refer to "Pop noise reduction functions".
NFPL, NFNL, NFPR, NFNR (Pin No.45, 44, 16, 17)
NFPL and NFNL are the digital amplifier feedback input terminals for left channel.
NFPR and NFNR are the digital amplifier feedback input terminals for right channel.
Connect the feedback signal of positive side and negative side of H-bridge configuration Power MOSFET output to
each terminal. At this time, as described in the "Example of application circuit", divide the voltage of feedback signal
with external resistor to prevent the maximum voltage from exceeding 5V and input to each terminal.
HP_L, HN_L, LP_L, LN_L, HP_R, HN_R, LP_R, LN_R (Pin No.34, 33, 31, 32, 27, 28, 30, 29)
HP_L, HN_L, LP_L and LN_L are Power MOSFET driving terminals for left channel.
HP_L is a driving output terminal for positive side P channel Power MOSFET (PMOS), HN_L is the one for positive
side N channel Power MOSFET (NMOS), LP_L is the one for negative side P channel Power MOSFET (PMOS),
and LN_L is the one for negative side N channel Power MOSFET (NMOS).
HP_R, HN_R, LP_R and LN_R are Power MOSFET driving terminals for right channel.
HP_R is a driving output terminal for positive side P channel Power MOSFET (PMOS), HN_R is the one for positive
side N channel Power MOSFET (NMOS), LP_R is the one for negative side P channel Power MOSFET (PMOS),
and LN_R is the one for negative side N channel Power MOSFET (NMOS).
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