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CX28C010NMB-15 View Datasheet(PDF) - Intersil

Part Name
Description
View to exact match
CX28C010NMB-15
Intersil
Intersil Intersil
CX28C010NMB-15 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
X28C010, X28HT010
Endurance and Data Retention
PARAMETER
Endurance
Endurance
Data Retention
MIN
10,000
100,000
100
MAX
UNIT
Cycles per byte
Cycles per page
Years
A.C. Conditions of Test
Input pulse levels
Input rise and fall times
Input and output timing levels
0V to 3V
10ns
1.5V
Mode Selection
CE OE WE
MODE
L
L
H
Read
L
H
L
Write
H
X
X
Standby and
Write Inhibit
X
L
X
Write Inhibit
X
X
H
Write Inhibit
I/O
DOUT
DIN
High Z
Equivalent A.C. Load Circuit
POWER
Active
Active
Standby
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5V
1.92kΩ
Output
1.37kΩ
100pF
AC Electrical Specifications Over the recommended operating conditions, unless otherwise specified.
X28C010-12
X28C010-15
X28C010-20,
X28HT010W
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX
READ CYCLE LIMITS
tRC
Read cycle time
tCE
Chip enable access time
tAA
Address access time
tOE
Output enable access time
tLZ (Note 4) CE LOW to active output
tOLZ (Note 4) OE LOW to active output
tHZ (Note 4) CE HIGH to high Z output
tOHZ (Note 4) OE HIGH to high Z output
tOH
Output hold from address change
120
150
200
120
150
200
120
150
200
50
50
50
0
0
0
0
0
0
50
50
50
50
50
50
0
0
0
X28C010-25
MIN MAX
UNIT
250
ns
250
ns
250
ns
50
ns
0
ns
0
ns
50
ns
50
ns
0
ns
11
FN8105.1
February 12, 2007
 

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