V6118 View Datasheet(PDF) - EM Microelectronic - MARIN SA
Part Name
Description
View to exact match
V6118 Datasheet PDF : 15 Pages
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R
V6118
Pin Assignment
Name
Function
S1..S40 LCD outputs, see Table 7
V3
LCD voltage bias level 3 (note 1, 2)
V2
LCD voltage bias level 2 (note 1)
V1
LCD voltage bias level 1 (note 1)
VLCD
FR
Power supply for the LCD
AC input signal for LCD driver output
DI
Serial data input
DO
Serial data output
CLK
Data clock input
STR
Data strobe, blank, synchronize input
VDD
Power supply for logic
COL
Column only driver mode
VSS
Supply GND
Table 9
Note 1: The V6118 has internal voltage bias level
generation. When driving large pixels, an external
resistor divider chain can be connected to the voltage
bias level inputs to obtain enhanced display contrast (see
Fig. 12, 13 and 14). The external resistor divider ratio
should be in accordance with the internal resistor ratio
(see Table 8).
Note 2: V3 is connected internally on the V6118 4.
Name COL inactive
S1
S2
S3
S4
S5
S6
S7
S8
S9…S40
V6118 (2)
Row1
Row2
Col1
Col2
Col3
Col4
Col5
Col6
Col7…38
V6118 (4)
Row1
Row2
Row3
Row4
Col1
Col2
Col3
Col4
Col5…36
V6118 (8)
Row1
Row2
Row3
Row4
Row5
Row6
Row7
Row8
Col1…32
COL
active
Col1
Col2
Col3
Col4
Col5
Col6
Col7
Col8
Col9…40
Table 7
LCD Voltage Bias Levels
LCD Drive
Type
LCD Bias
Configuration
VOP
(note 1)
VOFF (rms)
VON (rms)
VOFF (rms)
V6118 (2)
n=2
1:2 MUX
Alt + Pleshko
5 levels
2n = 3.69
1−
1
n
n + 1 = 2.41
n −1
V6118 (4)
n=4
1:4 MUX
1/3 Bias
4 Levels
3
1
+
8
n
= 1.73
V6118 (8)
n=8
1:8 MUX
Note 1: VOP = VLCD - VSS
Copyright © 2004, EM Microelectronic-Marin SA
1/4 Bias
5 Levels
6
4 = 3.4
1+
3
n
n + 15
n+3
= 1.446
Table 8
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