It is recommended that data transfer to the V6118 should
be synchronized to the FR signal to avoid a falling or
rising edge on the FR signal while writing data to the
V6118. The LCD pixels change polarity with the FR
signal. On the edges of the FR signal current spikes will
appear on the VSS and VLCD supply lines. If the supply
lines have high impedance then voltage spikes will
appear. These voltage spikes could interfere with data
loading on the DI and CLK pins.
Driver Outputs S1 to S40
There are 40 LCD driver outputs on the V6118. When
COL is inactive, the outputs S1 to Sn function as row
drivers and the outputs S(n+1) to S40 function as column
drivers, where n is the V6118 version no. (2, 4 or 8).
When COL is active, all 40 outputs function as column
drivers (see Table 6). There is a one to one relationship
between the display selected RAM and the LCD driver
outputs. Each pixel (segment) driven by the V6118 on the
LCD has a display RAM bit which corresponds to it.
Setting the bit turns the segment "on" and clearing it turns
The V6118 functions as a row and column driver while the
COL input is inactive. When active, the COL input
configures the V6118 to function as a column driver only.
The former row outputs function as column outputs. In
cascaded applications, one V6118 should be used in the
row and column configuration ( COL inactive) and the rest
as pure column drivers ( COL active) (see Fig. 10).
Note: when cascading V6118s never cascade one version
with another. If a V6118 8 is used to drive the rows, then
only V6118 8 can be cascaded with it. When COL is
active the V6118 needs 48 bits of data in a load cycle . 40
bits are used for the column data and 8 bits to address the
display RAM regardless of V6118 versions (2, 4or 8) (see
Fig.4, 5 and 10)
On power up the data in the shift registers, the two display
RAMs and the 40 bit display latches are undefined. The
STR input should be taken high on power up to blank the
display, then the display data written to the display
selected RAM (see Fig. 11). When finished the initial
write to the display selected RAM, take the STR input low
to display the display selected RAM contents (see also
section "STR Input").
Two V6118 8s Cascaded
By connecting the V1, V2 and V3 bias outputs as shown, the pixel load is averaged across all the drivers. The
effective bias level source impedance is the parallel combination of the total number of drivers. For example, if
two V6118 are cascaded as above, then the maximum bias level impedance becomes 12.5 kΩ.
Copyright © 2004, EM Microelectronic-Marin SA