STK11C68 View Datasheet(PDF) - Unspecified
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Description
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STK11C68 Datasheet PDF : 10 Pages
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STK11C68
SRAM READ CYCLES #1 & #2
(VCC = 5.0V + 10%)b
SYMBOLS
NO.
#1, #2
Alt.
1
tELQV
2
tAVAVg
3
tAVQVh
tACS
tRC
tAA
4
tGLQV
tOE
5
tAXQXh
tOH
6
tELQX
tLZ
7
tEHQZi
tHZ
8
tGLQX
tOLZ
9
tGHQZi
tOHZ
10
tELICCHf
tPA
11
tEHICCLe, f
tPS
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
20
25
35
45
ns
20
25
35
45
ns
22
25
35
45
ns
8
10
15
20
ns
5
5
5
5
ns
5
5
5
5
ns
7
10
13
15
ns
0
0
0
0
ns
7
10
13
15
ns
0
0
0
0
ns
25
25
35
45
ns
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledg
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
11
tEHICCL
7
tEHQZ
G
DQ (DATA OUT)
ICC
4
8
tGLQV
tGLQX
10
tELICCH
STANDBY
ACTIVE
9
tGHQZ
DATA VALID
June 1999
4-23
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