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ST24C01M6TR View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24C01M6TR SERIAL 1K (128 x 8) EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24C01M6TR Datasheet PDF : 16 Pages
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ST24/25C01, ST24C01R, ST24/25W01
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
Alt
Parameter
Min
Max
Unit
tCH1CH2
tR
Clock Rise Time
1
µs
tCL1CL2
tDH1DH2
tF
Clock Fall Time
tR
Input Rise Time
300
ns
1
µs
tDL1DL1
tCHDX (1)
tCHCL
tDLCL
tCLDX
tCLCH
tF
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
Input Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
300
ns
4.7
µs
4
µs
4
µs
0
µs
4.7
µs
tDXCX
tCHDH
tDHDL
tCLQV (2)
tSU:DAT
tSU:STO
tBUF
tAA
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
250
ns
4.7
µs
4.7
µs
0.3
3.5
µs
tCLQX
tDH
Data Out Hold Time
300
ns
fC
fSCL
Clock Frequency
100
kHz
tW (3)
tWR
Write Time
10
ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
6/16
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