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ST24C01M6TR View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24C01M6TR SERIAL 1K (128 x 8) EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24C01M6TR Datasheet PDF : 16 Pages
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ST24/25C01, ST24C01R, ST24/25W01
Figure 2A. DIP Pin Connections
ST24x01
ST25x01
ST24C01R
E0 1
E1 2
8 VCC
7 MODE/WC
E2 3
6 SCL
VSS 4
5 SDA
AI00840D
Figure 2B. SO Pin Connections
E0
E1
E2
VSS
ST24x01
ST25x01
ST24C01R
1
8
2
7
3
6
4
5
AI00841E
VCC
MODE/WC
SCL
SDA
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
TLEAD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
Unit
°C
°C
°C
VIO
Input or Output Voltages
–0.6 to 6.5
V
VCC
VESD
Supply Voltage
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
–0.3 to 6.5
V
4000
V
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 ).
3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont’d)
The ST24/25x01 are 1K bit electrically erasable
programmable memories (EEPROM), organized
as 128 x 8 bits. They are manufactured in SGS-
THOMSON’s Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C01R only.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus defini-
tion. This is used together with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 1K devices may be
attached to the I2C bus and selected individually.
The memories behave as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
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