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ST24C01M6TR View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24C01M6TR SERIAL 1K (128 x 8) EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24C01M6TR Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
ST24/25C01, ST24C01R, ST24/25W01
Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W01)
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01161B
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x01 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x01 terminate the
data transfer and switches to a standby state.
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